The present invention relates generally to a semiconductor memory and more particularly to a non-volatile semiconductor memory such as a non-volatile flash memory that may have an improved layout freedom.
It is a continuing goal to improve layout freedom of semiconductor devices. By doing so, chip size may be reduced and thus, manufacturing costs may be reduced.
FIG. 9 is a block diagram illustrating a plan view of a conventional non-volatile flash memory and given the general reference character 900.
Conventional non-volatile flash memory 900 is divided into two banks (B0 and B1). Bank B0 has four memory cell arrays (MCA00 to MCA03) arranged in quadrants to form a rectangular shape in a plan view. Bank B1 has four memory cell arrays (MCA10 to MCA13) arranged in quadrants to form a rectangular shape in a plan view. Each memory cell array (MCA00 to MCA03 and MCA10 to MCA13) contains 512 local bit lines LB and 512 word lines (not illustrated in FIG. 9). Memory cells are formed at intersections of bit lines LB and word lines.
Bank B0 has main X decoders (XDEC10, XDEC11, and XDEC20), and sub X decoders (XSUB00 to XSUB03) that are used to select a word line. Bank B1 has main X decoders (XDEC12, XDEC13, and XDEC21), and sub X decoders (XSUB10 to XSUB13) that are used to select a word line. Each memory cell array (MCA00 to MCA03 and MCA10 to MCA13) has a switch group (Y1S0 to Y1S3) located at ends of bit lines LB and connect local bit lines LB to main bit lines MB. A driver (Y1D0 to Y1D3) is adjacent to and drives a switch group (YS0 to YS3). A switch group (Y3S0 and Y3S1) is located between sense amplifier blocks SAB and main bit lines MB. A driver (Y3D0 and Y3D1) is located next to and drives a switch group (Y3S0 and Y3S1).
Referring now to FIG. 10, a circuit schematic diagram illustrating memory cell arrays (MCA00 to MCA03) of bank B0 is set forth.
In order to avoid unduly cluttering the figure, FIG. 10 only illustrates sixteen local bit lines LB and four main bit lines MB for each memory cell array (MCA00 to MCA03) of bank B0. Actually, each memory cell array (MCA00 to MCA03) has 512 local bit lines LB and there are 128 main bit lines MB disposed over each memory cell array (MCA00 to MCA03).
As illustrated in FIG. 10, memory cells MC are formed at intersections of local bit lines LB and word lines WL. Switch group Y1S0 includes transistors Tr1. Every other local bit line LB in memory cell arrays (MCA00 and MCA01) has an end connected to a transistor Tr1. Switch group Y1S1 includes transistors Tr2. Every other local bit line LB in memory cell arrays (MCA00 and MCA01) has an upper end connected to a transistor Tr2. In this way, every local bit line LB has a lower end connected to a transistor (Tr1 or Tr2) in a switch group (Y1S0 and Y1S1). In switch group Y1S0, two transistors Tr1 are connected to a main bit line MB. In switch group Y1S1, two transistors Tr2 are connected to a main bit line MB. In this way, one of four local bit lines LB are selectively connected to one main bit line MB through switch groups (Y1S0 and Y1S1).
Gates of transistors Tr1 in each switch group Y1S0 are connected to a driver Y1D0 through signal lines (D10 and D11). Signal line D10 is connected to the gate of one-half of transistors Tr1 in switch group Y1S0. Signal line D10 is connected to the gate of the other one-half of transistors Tr1 in switch group Y1S0. Switch groups (Y1S1 to Y1S3) are arranged in a similar manner. Drivers (Y1D0 to Y1D3) are respectively arranged between adjacent switch groups (YLS0 to Y1S3).
Switch group Y3S0 is disposed between main bit lines MB and sense amplifier blocks SAB. Switch group Y3S0 includes transistors Tr4. Each main bit line MB is connected to a source/drain of a transistor Tr4. The other source/drain of transistor Tr4 is connected to a sense amplifier SA in sense amplifier block SAB. Driver Y3D0 is commonly connected to gates of transistors Tr4 through signal line D30. Although only four transistors Tr4 are illustrated in each switch group Y3S0, there are 128 transistors Tr4 in each switch group or one transistor Tr4 for each main bit line MB. Bank B1 is similarly configured as bank B1. In bank B1 switch groups Y3S1 include transistors Tr4 having gates commonly connected to a driver Y3D1 through a signal line.
Referring now to FIG. 9, a DQ pad PAD1 is provided as a data I/O terminal and is connected to each sense amplifier block SAB. An input pad PAD2 receives an address signal and control signal. Conventional non-volatile flash memory 900 also includes a peripheral circuit P1 (an address buffer, for example), a peripheral circuit P2 (a power source generation circuit, for example), and a peripheral circuit P3 (such as a read-out and write-in control circuit, for example).
In conventional non-volatile flash memory 900, memory cell arrays (MCA00, MCA01, MCA10, and MCA11) can be simultaneously accessed because each memory cell array (MCA00, MCA01, MCA10, and MCA11) is connected to 128 sense amplifiers SA in sense amplifier block SAB. The 512 sense amplifiers SA in the four sense amplifier blocks SAB can then output data via DQ pad PAD1.
In conventional non-volatile flash memory 900, the 512 sense amplifiers SA are arranged in a row along the word line direction. Accordingly, the layout can be restricted in this area. As an example, because each main bit line MB is connected to a sense amplifier SA in sense amplifier block SAB, the sense amplifier SA must have a layout pitch no greater than the pitch of adjacent main bit lines MB.
In view of the above discussion, it would be desirable to provide a semiconductor memory device such as a non-volatile semiconductor memory that may have an increased layout freedom.
According to the present embodiments, a non-volatile flash memory that may have an improved layout freedom is disclosed. A non-volatile flash memory may include a plurality of banks. Each bank may include a plurality of memory cell arrays including a plurality of memory cells connected to sub bit lines. A plurality of sub bit lines may be selectively connected to a main bit line by a group switch. A group of main bit lines may be disposed over a memory cell array. A group of main bit lines may be selectively connected to a sense amplifier block by a group switch group and a bank switch group. In this way, a sense amplifier block may be shared by a plurality of groups of main bit lines. In this way, layout freedom may be improved.
According to one aspect of the embodiments, a non-volatile semiconductor memory device may include a first and second bank. Each bank may include a first and second memory cell array. Each of the first and second memory cell array may include nxc3x97k sub bit lines. N first main bit lines may be disposed over the first memory cell array. Each first main bit line may be coupled to k sub bit lines in the first memory cell array by a first sub bit line selecting circuit. N second main bit lines may be disposed over the second memory cell array. Each second main bit line may be coupled to k sub bit lines in the second memory cell array by a second sub bit line selecting circuit. A first sense amplifier block may include n sense amplifiers. A first main bit line selecting circuit may be coupled between the n first main bit lines of the first bank and the first sense amplifier block. A second main bit line selecting circuit may be coupled between the n second main bit lines of the first bank and the first sense amplifier block. The first main bit line selecting circuit may provide an electrical connection between each of the n first main bit lines of the first bank and a corresponding one of the n sense amplifiers when enabled. The second main bit line selecting circuit may provide an electrical connection between each of the n second main bit lines of the first bank and a corresponding one of the n sense amplifiers when enabled.
According to another aspect of the embodiments, a non-volatile semiconductor memory may include a second sense amplifier block. The second sense amplifier block may include n sense amplifiers. A third main bit line selecting circuit may be coupled between the n first main bit lines of the second bank and the second sense amplifier block. A fourth main bit line selecting circuit may be coupled between the n second main bit lines of the second bank and the second sense amplifier block. The third main bit line selecting circuit may provide an electrical connection between each of the n first main bit lines of the second bank and a corresponding one of the n sense amplifiers of the second sense amplifier block when enabled. The fourth main bit line selecting circuit may provide an electrical connection between each of the n second main bit lines of the second bank and a corresponding one of the n sense amplifiers of the second sense amplifier block when enabled.
According to another aspect of the embodiments, a non-volatile semiconductor memory device may include a third main bit line selecting circuit coupled between the n first main bit lines of the second bank and the first sense amplifier block. A fourth main bit line selecting circuit may be coupled between the n second main bit lines of the second bank and the first sense amplifier block. A first bank selecting circuit may be coupled in series with the first main bit line selecting circuit. The first bank selecting circuit may provide an electrical connection between the first main bit lines of the first bank and the sense amplifier block when enabled. A second bank selecting circuit may be couple in series with the third bit line selecting circuit. The second bank selecting circuit may provide an electrical connection between the first main bit lines of the second bank and the sense amplifier block when enabled. The third main bit line selecting circuit may provide an electrical connection between each of the n first main bit lines of the second bank and a corresponding one of the n sense amplifiers of the first sense amplifier block when enabled. The fourth main bit line selecting circuit may provide an electrical connection between each of the n second main bit lines of the second bank and a corresponding one of the n sense amplifiers of the first sense amplifier block when enabled.
According to another aspect of the embodiments, the first main bit line selecting circuit may be distributed in a first part and a second part. The first part may be located in a first region essentially at a first end of the sub bit lines of the first memory cell array and the second part may be located in a second region essentially at a second end of the sub bit lines of the first memory cell array.
According to another aspect of the embodiments, a non-volatile semiconductor memory device may include a plurality of global bit lines coupled between the first main bit line selecting circuit and the first sense amplifier block. The plurality of global bit lines may be divided into a first group of global bit lines and a second group of global bit lines. The first group of global bit lines may be disposed in a direction essentially perpendicular to the first main bit lines and may be coupled to the first part of the first main bit line selecting circuit. The second group of global bit lines may be disposed in a direction essentially perpendicular to the first main bit lines and may be coupled to the second part of the first main bit line selecting circuit.
According to another aspect of the embodiments, the first sense amplifier block may be disposed between the first and second banks.
According to another aspect of the embodiments, at least one of the first group of global bit lines may be formed over the first part of the first main bit line selecting circuit. At least one of the second group of global bit lines may be formed over the second part of the main bit line selecting circuit.
According to another aspect of the embodiments, each of the first and second banks may further include a third and fourth memory cell array. Each of the third and fourth memory cell arrays may include nxc3x97k sub bit lines. The n first main bit lines may be disposed over the third memory cell array. Each first main bit line may be coupled to k sub bit lines in the third memory cell array by a third sub bit line selecting circuit. The n second main bit lines may be disposed over the fourth memory cell array. Each second main bit line may be coupled to k sub bit lines in the fourth memory cell array by a fourth sub bit line selecting circuit.
According to another aspect of the embodiments, a semiconductor memory device may include a plurality of first main bit lines, a plurality of second main bit lines, a plurality of first sub bit line groups, and a plurality of second sub bit line groups. Each first sub bit line group may include a plurality of first sub bit lines corresponding to one of the plurality of first main bit lines. Each second sub bit line group may include a plurality of second sub bit lines corresponding to one of the plurality of second main bit lines. Each of the first sub bit lines and second sub bit lines may be connected to a plurality of memory cells. A first global bit line may be coupled to one of the first main bit lines and to one of the second main bit lines. A second global bit line may be coupled to another one of the first main bit lines and another one of the second main bit lines. A first sense amplifier may be coupled to the first global bit line. A second sense amplifier may be coupled to the second global bit line.
According to another aspect of the embodiments, the plurality of first and second main bit lines may be disposed in a first direction. The first and second global bit lines may be disposed in a second direction and may be separated by at least the plurality of first sub bit line groups. The first and second sense amplifiers may be arranged in the first direction.
According to another aspect of the embodiments, the first direction may be orthogonal to the second direction. A first connection transistor may provide an electrical connection between the one of the first main bit lines and the first global bit line. A second connection transistor may provide an electrical connection between the another one of the first main bit lines and the second global bit line. The first connection transistor may be separated by at lest one of the plurality of memory cells in the first direction from the second connection transistor.
According to another aspect of the embodiments, the first and second connection transistors may be insulated gate filed effect transistors (IGFETs).
According to another aspect of the embodiments, a non-volatile semiconductor memory device may include a first and second bank. Each of the first and second bank may include a first and second memory cell array. Each of the first and second memory cell arrays may include a plurality of sub bit lines arranged in a plurality of groups of sub bit lines. A plurality of main bit lines may be disposed over each of the first and second memory cell array. Each one of the plurality of main bit lines may be coupled to one of the plurality of groups of sub bit lines by a sub bit line selecting circuit. Each one of the plurality of main bit lines may be coupled to one of a plurality of sense amplifiers by a main bit line selecting circuit. One of the plurality of main bit lines may be disposed over the first memory cell array in the first bank may be coupled to the same one of the plurality of sense amplifiers as one of the plurality of main bit lines disposed over the second memory cell array in the first bank.
According to another aspect of the embodiments, the one of the plurality of main bit lines disposed over the first memory cell array in the first bank is coupled to the same one of the plurality of sense amplifiers as one of the plurality of main bit lines disposed over the first memory cell array in the second bank and one of the plurality of main bit lines disposed over the second memory cell array in the second bank.
According to another aspect of the embodiments, a global bit line may be commonly coupled to the one of the plurality of main bit lines disposed over the first memory cell array in the first bank, the one of the plurality of main bit lines disposed over the second memory cell array in the first bank, the one of the plurality of main bit lines disposed over the first memory cell array in the second bank, and the one of the plurality of main bit lines disposed over the second memory cell array in the second bank.
According to another aspect of the embodiments, the plurality of sense amplifiers may be disposed between the first and second banks.
According to another aspect of the embodiments, the main bit line selection circuit may include a group selection circuit and a bank selection circuit coupled in series between the each one of the plurality of main bit lines and the one of the plurality of sense amplifiers.
According to another aspect of the embodiments, the bank selection circuit and group selection circuit may be responsive to at least a portion of an address received by the non-volatile semiconductor memory device.
According to another aspect of the embodiments, the bank selection circuit may include a first insulated gate field effect transistor (IGFET). The group selection circuit may include a second IGFET. The first and second IGFETs may be coupled in series to provide a controllable impedance path between the each one of the plurality of main bit lines and the one of the plurality of sense amplifiers.
According to another aspect of the embodiments, the non-volatile semiconductor memory device is a flash memory. The non-volatile semiconductor memory device includes at least one erase circuit.